Analog Devices Inc. AD969x 14-Bit ADCs

Analog Devices AD9690, AD9691, AD9694, and AD9695 14-bit Analog-to-Digital Converters (ADC) are JESD204B ADCs designed for sampling wide bandwidth analog signals up to 2GHz. The devices include an on-chip buffer and sample-and-hold circuit for low power, small size, and ease-of-use. The low-power consumption ADC cores have a multistage, differential pipelined architecture with integrated, output-error correction logic. Each device includes wide bandwidth inputs to support a variety of user-selectable input ranges. The ADC data outputs are internally connected to two digital downconverters (DDCs). The DDC consists of four cascaded signal-processing stages, a 12-bit frequency translator (NCO), and four half-band decimation filters.

In addition to the DDC blocks, the AD969x ADCs offer several functions to simplify the Automatic Gain Control (AGC) function in the communications receiver. The programmable threshold detector enables monitoring of the incoming signal power using the fast-detect output bits of the ADC. Using the low-latency threshold indicator, designers can quickly turn down the system gain to avoid an overrange condition at the ADC input. Designers can configure the Subclass 1 JESD204B-based high-speed serialized output in a variety of one-, two-, four- or eight-lane configurations. The SYSREF± input pins support multiple device synchronization.

Features

Common Features
- JESD204B (Subclass 1) coded serial digital outputs
- 0.95V, 0.975V, 1.25V, 1.8V, 2.5V, 2.5V, or 3.3V DC supply operation
- No missing codes
- Amplitude detection bits for efficient AGC implementation
- 2 or 4 integrated wideband digital processors
- 12-bit or 48-bit NCO, up to 4 cascaded half-band filters
- Integer clock divide by 1, 2, 4,or 8
- Flexible JESD204B lane configurations
- Small signal dither
AD9690 Features
- 2.0W total power at 1GSPS (default settings)
- 1.5W total power at 500MSPS (default settings)
- Noise density = −154dBFS/Hz at 1GSPS
- SFDR = 85dBFS at 340MHz, 80dBFS at 985MHz
- SNR = 65.3dBFS at 340MHz (AIN = −1.0dBFS),
- 60.5dBFS at 985MHz
- ENOB = 10.8 bits at 10MHz
- DNL = ±0.5LSB
- INL = ±2.5LSB
- Internal ADC voltage reference
- Flexible Input Range
  - 1.46Vp-p to 1.94Vp-p (1.7Vp-p nominal) (for AD9690-1000)
  - 1.46Vp-p to 2.06Vp-p (2.06Vp-p nominal) (for AD9690-500)
- Programmable termination impedance: 400Ω, 200Ω, 100Ω, and 50Ω differential
- 2GHz usable analog input full power bandwidth
- Differential clock input
AD9691 Features
- 1.9W total power per channel (default settings for AD9691)
- SFDR = 77dBFS at 340MHz
- SNR = 63.4dBFS at 340MHz (AIN = −1.0dBFS)
- Noise density = −152.6dBFS/Hz
- 1.58Vp-p differential full scale input voltage
- Flexible termination impedance 400Ω, 200Ω, 100Ω, and 50Ω differential
- 1.5GHz usable analog input full power bandwidth
- 95dB channel isolation/crosstalk
- Timestamp feature

AD9694 Features
- Lane rates up to 15Gbps
- 1.66W total power at 500MSPS
- 415mW per ADC channel
- SFDR = 82dBFS at 305MHz (1.80Vp-p input range)
- SNR = 66.8dBFS at 305MHz (1.80Vp-p input range)
- Noise density = −151.5dBFS/Hz (1.80Vp-p input range)
- Internal ADC voltage reference
- Analog input buffer
- On-chip dithering to improve small-signal linearity
- Flexible differential input range
  - 1.44Vp-p to 2.16Vp-p (1.80Vp-p nominal)
- 1.4GHz analog input full power bandwidth
- Differential clock input
- On-chip temperature diode
- Flexible JESD204B lane configurations
AD9695 Features
- Lane rates up to 16Gbps
- 1.6W total power at 1300MSPS
  - 800mW per ADC channel
- SFDR = 65.6dBFS at 175MHz (1.59Vp-p input range)
- SNR = 78dBFS at 172.3MHz (1.59Vp-p input range)
- Noise density =
  - -153.9dBFS/Hz (1.59Vp-p input range)
  - -155.6dBFS/Hz (2.04Vp-p input range)
- Internal ADC voltage reference
- Flexible differential input range
  - 1.36Vp-p to 2.04Vp-p (1.59Vp-p nominal)
- 2GHz analog input full power bandwidth
- 95dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- 2 integrated digital downconverters per ADC channel
  - 48-bit NCO
  - Programmable decimation rates
- Differential clock input
- On-chip dithering to improve small-signal linearity

Applications

Communications
Multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
General-purpose software radios
Ultra-wideband satellite receivers
Instrumentation (oscilloscopes, spectrum analyzers, network analyzers, integrated RF test solutions)
Radars

Electronic support measures, electronic countermeasures, and electronic counter-countermeasures
Signals intelligence (SIGINT)
DOCSIS 3.x CMTS upstream receive paths
HFC digital reverse path receivers
High-speed data acquisition systems
Hybrid fiber-coaxial digital reverse path receivers
Wideband digital predistortion